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ISL43L841
Data Sheet June 30, 2006 FN6212.1
Ultra Low ON-Resistance, Low-Voltage, Single Supply, Differential 4 to 1 Analog Multiplexer
The Intersil ISL43L841 device contains precision, bidirectional, analog switches configured as a differential 4-channel multiplexer/demultiplexer. It is designed to operate from a single +1.65V to +4.5V supply. The device has an inhibit pin to simultaneously open all signal paths. With a supply voltage of 4.2V and logic high voltage of 2.85V at the logic inputs, the part draws only 20A max of ICC current. ON resistance is 0.47 with a +4.3V supply and 0.65 with a single +1.8V supply. Each switch can handle rail to rail analog signals. A channel can handle 300mA of continuous current. The part has low quiescent power consumption of 0.23W max. All digital inputs are 1.8V logic-compatible when using a single +3V supply. The ISL43L841 is a differential 4 to 1 multiplexer device that is offered in a 16 Ld 3x3 TQFN package. Table 1 summarizes the performance of this family.
TABLE 1. FEATURES AT A GLANCE CONFIGURATION 4.3V RON 4.3V tON/tOFF 3V RON 3V tON/tOFF 1.8V RON 1.8V tON/tOFF PACKAGES Diff 4:1 Mux 0.47 22ns/12ns 0.52 25ns/15ns 0.65 40ns/17ns 16 Ld 3x3 TQFN
Features
* Pb-Free Plus Anneal (RoHS Compliant) * Pin Compatible Replacement for the MAX4782 and MAX4618 * ON Resistance (RON) - V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.47 - V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.52 - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65 * RON Matching Between Channels. . . . . . . . . . . . . . . . 0.12 * RON Flatness Across Signal Range . . . . . . . . . . . . . 0.056 * Single Supply Operation. . . . . . . . . . . . . . . . +1.65V to +4.5V * Low Power Consumption (PD). . . . . . . . . . . . . . . . . <0.23W * Low ICC Current when VinH is not at the V+ Rail * Fast Switching Action (VS = +3V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns * Guaranteed Break-Before-Make * High Current Handling Capacity (300mA Continuous) * Available in 16 Ld 3x3 TQFN * 1.8V CMOS-Logic Compatible (+3V Supply)
Applications
* Battery Powered, Handheld, and Portable Equipment - Cellular/Mobile Phones - Pagers - Laptops, Notebooks, Palmtops * Portable Test and Measurement * Medical Equipment * Audio and Video Switching
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches"
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL43L841 Pinout
(Note 1) ISL43L841 (3x3 TQFN) TOP VIEW
A2 A0 B2 13 V+ 14
16
15
COMA
1
12
B1
A3
2
11
COMB
A1
3 LOGIC
10
B0
INH
4
9
B3
5 N.C.
6 GND
7 ADD0
8 ADD1
NOTE: 1. Switches Shown for Logic "0" Inputs.
Truth Table
ISL43L841 INH 1 0 0 0 0 ADD0 X 0 0 1 1 ADD1 X 0 1 0 1 SWITCH ON NONE A0, B0 A1, B1 A2, B2 A3, B3
Ordering Information
PART NO. ISL43L841IRZ (Note) TEMP. RANGE PART (C) MARKING L81Z PACKAGE PKG. DWG. #
-40 to 85 16 Ld 3x3 TQFN L16.3x3A (Pb-Free) -40 to 85 16 Ld 3x3 TQFN L16.3x3A Tape and Reel (Pb-Free)
ISL43L841IRZ-T L81Z (Note)
NOTE: Logic "0" 0.5V. Logic "1" 1.4V, with a 3V supply. X = Don't Care.
Pin Descriptions
PIN V+ N.C. GND INH COMA COMB A0-A3 B0-B3 ADDx FUNCTION System Power Supply Input (1.65V to 4.5V) N0 Connect. Not internally connected. Ground Connection Inhibit Input Pin. Connect to GND for Normal Operation. Connect to V+ to turn all switches off. Analog Switch Channel A Output Analog Switch Channel B Output Analog Switch Channel A Input Analog Switch Channel B Input Address Input Pin
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN6212.1 June 30, 2006
ISL43L841
Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V Input Voltages INH, Ax, Bx, ADDx (Note 2) . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V Output Voltages COMx (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V Continuous Current NO or COM . . . . . . . . . . . . . . . . . . . . . 300mA Peak Current NO or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 500mA ESD Rating HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4kV
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) 16 Ld 3x3 TQFN Package . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature (Plastic Package). . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C (Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 2. Signals on Ax, Bx, COMx, ADDx, or INH exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379.
Electrical Specifications - 4.3V Supply Test Conditions: VSUPPLY = +3.9V to +4.5V, GND = 0V, VINH = 1.4V, VINL = 0.4V
(Notes 4, 8), Unless Otherwise Specified PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 3.9V, ICOM = 100mA, VAX or VBX = 0V to V+, (See Figure 5) V+ = 3.9V, ICOM = 100mA, VAX or VBX = Voltage at max RON, (Note 6) V+ = 3.9V, ICOM = 100mA, VAX or VBX = 0V t0 V+, (Note 7) V+ = 4.5V, VCOM = 0.3V, 3V, VAX or VBX = 3V, 0.3V Full 25 Full 25 Full 25 Full 25 Full V+ = 4.5V, VCOM = VAX or VBX = 0.3V, 3V 25 Full 0 -50 -150 -50 -150 0.48 0.56 0.12 0.13 0.056 0.06 1 0.6 V+ 50 150 50 150 V nA nA nA nA TEST CONDITIONS TEMP (C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
Ax or Bx OFF Leakage Current, IAx(OFF) or IBx(OFF) COM ON Leakage Current, ICOM(ON)
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON V+ = 3.9V, VAx or VBx = 3.0V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 3.9V, VAx or VBx = 3.0V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 3.9V, VAX or VBX = 3.0V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 4.5V, VAX or VBX = 3.0V, RL = 50, CL = 35pF, (See Figure 3, Note 10) 25 Full 25 Full 25 Full 25 Full 1 24 14 21 4 34 38 24 28 31 34 ns ns ns ns ns ns ns ns V+ = +4.5V, VINH = VADD = 0V or V+ (Note 10) Full Full Full 1.5 -0.5 1.07 0.86 0.4 0.5 V V A
Inhibit Turn-OFF Time, tOFF
Address Transition Time, tTRANS
Break-Before-Make Time, tBBM
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ISL43L841
Electrical Specifications - 4.3V Supply Test Conditions: VSUPPLY = +3.9V to +4.5V, GND = 0V, VINH = 1.4V, VINL = 0.4V
(Notes 4, 8), Unless Otherwise Specified (Continued) PARAMETER Input OFF Capacitance, COFF COM OFF Capacitance, COFF COM ON Capacitance, CCOM(ON) OFF Isolation Crosstalk, Note 9 Total Harmonic Distortion (THD) TEST CONDITIONS f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) RL = 50, CL = 35pF, f = 100kHz, (See Figures 4 and 6) f = 20Hz to 20kHz, 0.5Vp-p, RL = 32 TEMP (C) 25 25 25 25 25 25 (NOTE 5) MIN TYP 62 218 232 65 -100 0.02 (NOTE 5) MAX UNITS pF pF pF dB dB %
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 4.5V, VINH, VADD = 0V or V+, Switch On or Off Full 25 Full Positive Supply Current, I+ NOTES: 4. VIN = Input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. RON matching between channels is calculated by subtracting the channel with the highest max RON value from the channel with lowest max RON value. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Parts are 100% tested at +25C. Limits across the full temperature range are guaranteed by design and correlation. 9. Between any two switches. 10. Guaranteed but not tested. V+ = 4.2V, VADDx = 2.85V 25 1.65 0.02 10 4.5 0.05 0.9 20 V A A A
Electrical Specifications - 3V Supply
Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.4V (Notes 4, 8) Unless Otherwise Specified TEST CONDITIONS TEMP (C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 2.7V, ICOM = 100mA, VAX or VBX = 0V to V+, See Figure 5 V+ = 2.7V, ICOM = 100mA, VAX or VBX = Voltage at max RON, (Note 6) V+ = 2.7V, ICOM = 100mA, VAX or VBX = 0V t0 V+, (Note 7) 25 Full 25 Full 25 Full
0 -
0.53 0.12 0.056 -
V+ 0.75 0.8 0.2 0.2 0.15 0.15
V
RON Matching Between Channels, DRON RON Flatness, RFLAT(ON)
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON V+ = 2.7V, VAx or VBx = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 2.7V, VAx or VBx = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 10) 25 Full 25 Full 27 16 37 41 26 30 ns ns ns ns V+ = 3.6V, VINH = VADD = 0V or V+ (Note 10) Full Full Full 1.4 -0.5 0.8 0.67 0.4 0.5 V V A
Inhibit Turn-OFF Time, tOFF
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FN6212.1 June 30, 2006
ISL43L841
Electrical Specifications - 3V Supply
Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.4V (Notes 4, 8) Unless Otherwise Specified (Continued) TEST CONDITIONS V+ = 2.7V, VAX or VBX = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 3.3V, VAX or VBX = 1.5V, RL = 50, CL = 35pF, (See Figure 3, Note 10) CL = 1.0nF, VG = 0V, RG = 0W, (See Figure 2) f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) RL = 50, CL = 35pF, f = 100kHz, (See Figures 4 and 6) f = 20Hz to 20kHz, 0.5Vp-p, RL = 32 TEMP (C) 25 Full 25 Full 25 25 25 25 25 25 25 (NOTE 5) MIN 1 TYP 24 4 -65 62 218 232 65 -100 0.02 (NOTE 5) MAX UNITS 34 38 ns ns ns ns pC pF pF pF dB dB %
PARAMETER Address Transition Time, tTRANS
Break-Before-Make Time, tBBM
Charge Injection, Q Input OFF Capacitance, COFF COM OFF Capacitance, COFF COM ON Capacitance, CCOM(ON) OFF Isolation Crosstalk, (Note 9) Total Harmonic Distortion (THD)
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 3.6V, VINH, VADD = 0V or V+, Switch On or Off Full 25 Full 1.65 4.5 0.05 0.9 V A A
Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Notes 4, 8),
Unless Otherwise Specified PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 1.8V, ICOM = 10.0mA, VAX or VBX = 1.0V, (See Figure 5) V+ = 1.8V, ICOM = 10.0mA, VAX or VBX = 1.0V, (See Figure 5) V+ = 1.8V, ICOM = 10.0mA, VAX or VBX = 0V, 0.9V, 1.6V, (See Figure 5) Full 25 Full 25 Full 25 Full 0 0.65 0.12 0.12 0.14 0.14 V+ 0.85 0.9 V TEST CONDITIONS TEMP (C) MIN (NOTE 5) TYP MAX (NOTE 5) UNITS
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON V+ = 1.8V, VAx or VBx = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 1.8V, VAx or VBx = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 1.8V, VAX or VBX = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 1.8V, VAX or VBX = 1.0V, RL = 50, CL = 35pF, (See Figure 3, Note 10) CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) 25 Full 25 Full 25 Full 25 25 40 17 32 9 -39 50 55 27 31 42 46 ns ns ns ns ns ns ns pC V+ = 1.8V, VINH, VADD = 0V or V+, (Note 10) Full Full Full 1 -0.5 0.4 0.5 V V A
Inhibit Turn-OFF Time, tOFF
Address Transition Time, tTRANS
Break-Before-Make Time, tBBM Charge Injection, Q
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FN6212.1 June 30, 2006
ISL43L841 Test Circuits and Waveforms
C V+ LOGIC INPUT 50% 0V tON tr < 5ns tf < 5ns V+ A0, B0 A1, A2, B1, B2, A3, B3 INH VA0, VB0 SWITCH OUTPUT 90% VOUT 90% LOGIC INPUT COMA COMB VOUT V+ C
GND ADD0-1
RL 50
CL 35pF
0V tOFF
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1B. INHIBIT tON/tOFF TEST CIRCUIT
FIGURE 1A. INHIBIT tON/tOFF MEASUREMENT POINTS
V+ LOGIC INPUT 0V tTRANS 50%
tr < 5ns tf < 5ns
C
V+
C
V+
A0, B0 A1, A2, B1, B2, A3, B3 COMA, COMB INH RL 50 VOUT
VA0, VB0 SWITCH OUTPUT
VOUT
90% ADD0-1 GND LOGIC INPUT CL 35pF
10% VA3, VB3 tTRANS
0V
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1D. ADDRESS tTRANS TEST CIRCUIT
FIGURE 1C. ADDRESS tTRANS MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
V+ C
V+ LOGIC INPUT OFF ON OFF 0V VG
RG 0
Ax, Bx ADD1 ADD0
VOUT COMA, COMB
SWITCH OUTPUT VOUT Q = VOUT x CL
VOUT
CHANNEL SELECT
GND
INH LOGIC INPUT
CL 1000pF
Repeat test for other switches. FIGURE 2B. Q TEST CIRCUIT FIGURE 2. CHARGE INJECTION
FIGURE 2A. Q MEASUREMENT POINTS
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FN6212.1 June 30, 2006
ISL43L841 Test Circuits and Waveforms (Continued)
V+ LOGIC INPUT 0V V+ 90% LOGIC INPUT tBBM GND INH A0-A3 B0-B3 ADD0-1 COMA COMB VOUT RL 50 CL 35pF tr < 5ns tf < 5ns V+ C C
SWITCH OUTPUT VOUT 0V
FIGURE 3A. tBBM MEASUREMENT POINTS
Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3B. tBBM TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
V+ 10nF
V+
C
SIGNAL GENERATOR
Ax or Bx
RON = V1/100mA Ax or Bx 0V or V+ ADD1 ADD0 VX 100mA CHANNEL SELECT GND INH V1 COMA or COMB GND 0V or V+ ADD1 ADD0 CHANNEL SELECT INH
ANALYZER RL
COMx
Off-Isolation is measured between COM and "Off" NO terminal on each switch. Signal direction through switch is reversed and worst case values are recorded.
FIGURE 4. OFF ISOLATION TEST CIRCUIT
V+
FIGURE 5. RON TEST CIRCUIT
C V+ C 0V or V+
SIGNAL GENERATOR
Ax 0V or V+ CHANNEL SELECT
50 COMA Ax or Bx
ADD1 ADD0 Bx N.C.
IMPEDANCE ANALYZER
ADD1 ADD0 COMA or COMB GND INH CHANNEL SELECT
ANALYZER RL
COMB
GND
INH
Crosstalk is measured between adjacent channels with one channel ON and the other channel OFF. Signal direction through switch is reversed and worst case values are recorded.
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
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FN6212.1 June 30, 2006
ISL43L841 Detailed Description
The ISL43L841 analog multiplexer offers precise switching capability from a single 1.65V to 4.5V supply with low onresistance (0.47) and high speed operation (tON = 24ns, tOFF = 14ns). The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (1.65V), low power consumption (0.23W), low leakage currents (50nA max). High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection.
Power-Supply Considerations
The ISL43L841 construction is typical of most CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL43L841 4.7V maximum supply voltage provides plenty of room for the 10% tolerance of 4.3V supply, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.65V but the part will operate with a supply below 1.65V. It is important to note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance Curves for details. V+ and GND power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switch V+ and GND signals to drive the analog switch gate terminals. This device cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pins and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the V+ rail. Logic inputs can be protected by adding a 1k resistor in series with the logic input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the submicroamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch. Connecting schottky diodes to the signal pins as shown in Figure 8 will shunt the fault current to the supply or to ground thereby protecting the switch. These schottky diodes must be sized to handle the expected fault current.
OPTIONAL SCHOTTKY DIODE OPTIONAL PROTECTION RESISTOR V+ ADDX INH VCOM
Logic-Level Thresholds
These devices are 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2.5V to 4.5V (see Figure 15). At 2.5V the VINL level is about 0.52V. This is still above the 1.8V CMOS guaranteed minimum level of 0.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. The ISL43L841 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0V to V+). For example driving the device with 2.85V logic (0V to 2.85V) while operating with a 4.2V supply, the device draws only 10A of current when both address inputs are high (see Figure 13 for VLOGIC = 2.85V).
High-Frequency Performance
In 50 systems, signal response is reasonably flat even past 10MHz with a -3dB bandwidth of 70MHz (see Figure 19). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch's input to its output. Off Isolation is the resistance to this feed through, while Crosstalk indicates the amount of feed through from one switch to another. Figure 20 details the high Off Isolation and Crosstalk rejection provided by this family. At 100kHz, Off Isolation is about 65dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection
FN6212.1 June 30, 2006
VNOx
GND OPTIONAL SCHOTTKY DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
8
ISL43L841
due to the voltage divider action of the switch OFF impedance and the load impedance. they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced,
Typical Performance Curves TA = 25C, Unless Otherwise Specified
0.75 V+ = 1.65V 0.7 0.65 0.5 RON () V+ = 1.8V 0.55 0.5 0.45 0.4 0 1 2 VCOM (V) 3 4 5 V+ = 2.7V V+ = 3V V+ = 3.6V V+ = 4.3V 0.3 0 1 2 VCOM (V) 3 4 5 RON () 0.6 85C ICOM = 100mA 0.55 0.6 V+ = 4.3V ICOM = 100mA
0.45 25C 0.4
0.35
-40C
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
0.65 V+ = 3V ICOM = 100mA 0.6
0.75 V+ = 1.8V ICOM = 100mA 0.7 0.65
0.55 RON () 85C 0.5 25C 0.5 0.4 -40C 0.35 0 0.5 1 1.5 VCOM (V) 2 2.5 3 0.45 RON () 0.6 0.55
85C
25C
0.45
-40C 0.4 0 0.5 1 VCOM (V) 1.5 2
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. ON RESISTANCE vs SWITCH VOLTAGE
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FN6212.1 June 30, 2006
ISL43L841 Typical Performance Curves TA = 25C, Unless Otherwise Specified (Continued)
50 V+ = 4.2V 40 SWEEPING TWO LOGIC INPUTS 30 iV+ (A) Q (pC) -10 -20 -30 V+ = 1.8V -40 -50 -60 -70 -80 V+ = 3V -90 -100 0 0 1 2 VLOGIC (V) 3 4 5 -110 0 0.5 1 1.5 VCOM (V) 2 2.5 3
20 SWEEPING ONE LOGIC INPUT
10
FIGURE 13. I+ CURRENT vs LOGIC VOLTAGE
FIGURE 14. CHARGE INJECTION vs SWITCH VOLTAGE
1.3 1.2 1.1 1 VINH AND VINL (V) VINH tRANS (ns) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 1 1.5 2 2.5 3 V+ (V) 3.5 4 4.5 VINL
200
150
100
50
85C -40C
25C
0
1
1.5
2
2.5 3 V+ (V)
3.5
4
4.5
FIGURE 15. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 16. ADDRESS TRANS TIME vs SUPPLY VOLTAGE
140 120 100 tOFF (ns) tON (ns) 80 60 85C 40 -40C 20 0 1 1.5 2 2.5 3 V+ (V) 3.5 4 4.5
40 35 30 25 20 15 -40C 10 5 1 1.5 2 2.5 V+ (V) 3 3.5 4 4.5 85C 25C
25C
FIGURE 17. INHIBIT TURN - ON TIME vs SUPPLY VOLTAGE
FIGURE 18. INHIBIT TURN - OFF TIME vs SUPPLY VOLTAGE
10
FN6212.1 June 30, 2006
ISL43L841 Typical Performance Curves TA = 25C, Unless Otherwise Specified (Continued)
NORMALIZED GAIN (dB) 0 V+ = 3V 0 -10 CROSSTALK (dB) -10 GAIN -20 -30 0 20 40 PHASE () 60 80 RL = 50 VIN = 0.2VP-P to 2VP-P 0.1M 1M 10M FREQUENCY (Hz) 450 -50 ISOLATION -60 -70 -80 CROSSTALK -90 -100 1k 100 110 100M 500M 70 80 90 30 OFF ISOLATION (dB) 40 50 60 V+ = 3V 20 10
PHASE
100 100M
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 19. FREQUENCY RESPONSE
FIGURE 20. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND (QFN Paddle Connection: To Ground or Float) TRANSISTOR COUNT: 228 PROCESS: Si Gate CMOS
11
FN6212.1 June 30, 2006
ISL43L841 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP)
)
2X A 9 D1 D1/2 6 INDEX AREA N 1 2 3 E1/2 E1 9 2X 0.15 C B 2X 0.15 C A 4X 0 TOP VIEW A2 B E/2 E 2X 0.15 C B D D/2 0.15 C A
L16.3x3A
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E 1.35 0.18 MIN 0.70 NOMINAL 0.75 0.20 REF 0.23 3.00 BSC 2.75 BSC 1.50 3.00 BSC 2.75 BSC 1.35 1.50 0.50 BSC 0.20 0.30 0.40 16 4 4 0.60 12 0.50 1.65 1.65 0.30 MAX 0.80 0.05 0.80 NOTES 9 9 5, 8 9 7, 8, 10 9 7, 8, 10 8 2 3 3 9 9 Rev. 0 6/04
A
/ / 0.10 C 0.08 C
E1 E2 e k L
C A3 A1
SEATING PLANE
SIDE VIEW NX b 5
9
4X P D2 (DATUM B) 4X P D2 2N
0.10 M C A B 7 8 NX k
N Nd Ne P
(Ne-1)Xe REF.
1 (DATUM A) 6 INDEX AREA NX L Ne 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 2 3 E2 7 E2/2 8
NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.
9 CORNER OPTION 4X
SECTION "C-C" C L C L
8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
L
L1 CC e
10
L L1 e
10
9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2 and D2 MAX dimension.
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN6212.1 June 30, 2006

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